1. Field of the Invention
Embodiments of the present invention relate to semiconductor technology, and more particularly, to a method for fabricating a capacitor and a capacitor structure thereof.
2. Description of Prior Art
One technique for vertically interconnecting chips is through silicon vias (TSV). Through silicon vias are connections through the substrate of the chips and may be used to connect a layer of chips on one side of the substrate to an opposite side of the substrate. Different from IC wire-bonding and stud-bump bonding technology, the TSV technique maximizes the density of stacked chips in three dimensional directions, minimizes overall area, and significantly improves the chip interconnect speed and power consumption performance.
A method for forming a TSV is via first technology, wherein before fabricating metal layers of a semiconductor chip, a via is formed through a chip substrate, and the via is electrically connected with a metal layer near the substrate of the chip; then, feedthrough connections are added for obtaining a low resistive path to active components on the substrate. In other words, multiple through-silicon vias can be fabricated to provide electric power to another chip.
Another method for forming TSV is via last technology. In the via last technology, a metal layer is first formed on the substrate of the chip; then a TSV is formed through the substrate and metal layers. The via last method allows a straight line path through the semiconductor chip, so that there is no need for additional metal layers.
In conventional art, regardless how a TSV is formed, either through via first technology or via last technology, at least an interconnect capacitor should be fabricated in the substrate as decoupling capacitor. Generally, the interconnect capacitor is a parallel-plate capacitor. Specifically, the parallel-plate capacitor is fabricated by successively forming a metal layer, an insulator layer, and a metal layer on the substrate, which forms an interconnect capacitor. However, this conventional metal-insulation-metal (MIM) capacitor requires substantial silicon area for large capacitance values.
Therefore, there is a need for a method of fabricating interconnect capacitor between chips that can use silicon area more efficiently to provide a high capacitance value.